The present invention relates to a semiconductor device, and more particularly to an SOI-MOS field effect transistor.
Semiconductor devices having silicon-on-insulator substrate structures are attractive as being suitable for easy isolation of device and high integration. The SOI semiconductor devices are also free from the problems with latch up phenomenon. The SOI semiconductor devices are further advantageous in those low junction capacitance of the source/drain regions which allows a high speed performance. Such the SOI semiconductor devices are superior than bulk type semiconductor devices in the above described advantages.
Typical one of the conventional SOI-MOS field effect transistors will be described with reference to FIG. 1. A buried silicon oxide layer 2 is provided on a silicon substrate 1. A silicon-on-insulator layer made of silicon is selectively provided on the buried silicon oxide layer 2 so that the silicon-on-insulator layer is electrically isolated by the buried silicon oxide layer 2 from the silicon substrate 1. The silicon-on-insulator layer comprises an n+-type drain region 3, a p--type channel region 5 and an n+-type source region 4. A gate insulation film 7 is selectively provided on the channel region 5. A gate electrode 8 is provided on the gate insulation film 7. Side wall oxide films 9 are provided on opposite sides of the gate electrode 8. An inter-layer insulator 10 is provided which covers the source and drain regions 4 and 3 and the gate electrode 8 with the side wall oxide films 9. Metal interconnections 11 are provided which extend over the inter-layer insulator 10. Contact holes are formed in the inter-layer insulator 10 and over the source and drain regions 4 and 3 and under the metal interconnections 11 so that the contact holes reach the source and drain regions 4 and 3. Contact layers electrically conductive are provided within the contact holes so that the contact layers provide electrical connections between the source/drain regions 4 and 3 and the metal interconnections 11. Namely, the source/drain regions 4 and 3 are electrically connected through the contact layers in the contact holes to the metal interconnections 11.
The source region is applied with a ground voltage whilst the gate electrode 8 and the drain region 3 are applied with positive voltages. If the drain voltage is risen, then a field applied to the junction portion between the drain region 3 and the channel region 5 is increased so that electron-hole pairs are generated at the junction portion between the drain region 3 and the channel region 5. Electrons generated are absorbed by the drain region 4 whilst holes generated are absorbed by the source region 4 but partially. Namely, only a part of the holes generated is absorbed by the source region 4, whilst the remaining part of the holes generated is therefore accumulated in the channel region 5. The accumulation of the holes generated in the channel region 5 results in the increase in potential of the channel region 5. The increase in potential of the channel region 5 results in the drop of the threshold voltage of the device. The increase in potential of the channel region 5 may also cause kink effect which causes a rapid increase in drain current by an application of the drain voltage.
If the drain voltage is furthermore risen, an increase is caused for a ratio of electron injection from the source region 4 into the channel region 5 whereby the field effect transistor enters into a parasitic bipolar transistor operating region wherein the drain current is rapidly increased and further a high voltage characteristic of the field effect transistor is deteriorated. Such the kink effect and the parasitic bipolar transistor operating phenomenon of the field effect transistor provide a remarkable distortion of the output waveform of the field effect transistor.
Since, as described above, the kink effect parasitic bipolar transistor operating phenomenon are caused by the accumulation of holes in the channel region 5, it is required for suppressing the kink effect parasitic bipolar transistor operating phenomenon to discharge the holes from the channel region 5. The above SOI-MOS field effect transistors had been improved to discharge the holes from the channel region 5.
A second conventional SOI-MOS field effect transistor will be described with reference to FIG. 2. This second conventional SOI-MOS field effect transistor is also disclosed in Japanese laid-open Patent Publication No. 2-280371. A silicon-on-insulator layer made of silicon is selectively provided on the buried silicon oxide layer 2 so that the silicon-on-insulator layer is electrically isolated by the buried silicon oxide layer 2 from the silicon substrate 1. The silicon-on-insulator layer comprises p+-type high impurity concentration regions 6, an n+-type drain region 3 laminated on the p+-type high impurity concentration region 6, a p--type channel region 5 and an n+-type source region 4 laminated on the p+-type high impurity concentration region 6. A gate insulation film 7 is selectively provided on the channel region 5. A gate electrode 8 is provided on the gate insulation film 7. Side wall oxide films 9 are provided on opposite sides of the gate electrode 8. An inter-layer insulator 10 is provided which covers the source and drain regions 4 and 3 and the gate electrode 8 with the side wall oxide films 9. Metal interconnections 11 are provided which extend over the inter-layer insulator 10. Source and drain contact holes are formed in the inter-layer insulator 10 and over the source and drain regions 4 and 3 respectively and under the metal interconnections 11 so that the source contact hole penetrates through the source region 4 to reach the p+-type high impurity concentration region 6 under the source region 4 whilst the drain contact hole reaches to the top surface of the drain region 3. Source and drain contact layers electrically conductive are provided within the source and drain contact holes respectively so that the source contact layer not only provides an electrical connection between the metal interconnection 11 and the source region 4 but also provides a short circuit between the p+-type high impurity concentration region 6 and the source region 4 whereby a current path is formed from the channel region 5 through the p+-type high impurity concentration region 6 and the source contact layer to the metal interconnection 11. The current path allows the holes generated in the channel region 5 to withdraw or discharge through the p+-type high impurity concentration region 6 and the source contact layer to the metal interconnection 11.
The above second conventional SOI-MOS field effect transistor is, however, engaged with the following problems and disadvantages. As described above, the short circuit is formed between the p+-type high impurity concentration region 6 and the source region 4, a potential of the p+-type high impurity concentration region 6 is fixed at the source potential of the source region 4. Further, the p+-type high impurity concentration region 6 is of the same conductivity type as the channel region 5, for which reason a potential of the channel region 5 is fixed at the same potential as the source potential of the source region 4. This means it difficult to control the source potential independently so as to control the threshold voltage of the field effect transistor. Furthermore, the drain region 3 has a large area of p-n junction with the p+-type high impurity concentration region 6, for which reason a large parasitic capacitance is formed at the p-n junction between the drain region 3 and the p+-type high impurity concentration region 6.
A third conventional SOI-MOS field effect transistor will be described with reference to FIG. 3. This third conventional SOI-MOS field effect transistor is also disclosed in Japanese laid-open Patent Publication No. 4-259259. A silicon-on-insulator layer made of silicon is selectively provided on the buried silicon oxide layer 2 so that the silicon-on-insulator layer is electrically isolated by the buried silicon oxide layer 2 from the silicon substrate 1. The silicon-on-insulator layer comprises an n+-type drain region 3, a p--type channel region 5, a p+-type high impurity concentration region 6, a p--type low impurity concentration region 5a between the channel region 5 and the p+-type high impurity concentration region 6, and an n+-type source region 4 laminated on the p--type low impurity concentration region 5a. A gate insulation film 7 is selectively provided on the channel region 5. A gate electrode 8 is provided on the gate insulation film 7. Side wall oxide films 9 are provided on opposite sides of the gate electrode 8. An inter-layer insulator 10 is provided which covers the source and drain regions 4 and 3 and the gate electrode 8 with the side wall oxide films 9. Metal interconnections 11 are provided which extend over the inter-layer insulator 10. Source and drain contact holes are formed in the inter-layer insulator 10 and over the source and drain regions 4 and 3 respectively and under the metal interconnections 11 so that the drain and drain contact holes reach the top surfaces of the source and drain regions 4 and 3. Further, an additional contact hole is formed in the inter-layer insulator 10 and over the p+-type high impurity concentration region 6 and under the metal interconnection 11 so that the additional contact hole reaches the top surface of the p+-type high impurity concentration region 6. Source and drain contact layers electrically conductive are provided within the source and drain contact holes respectively so that the source and drain contact layers provide electrical connections between the metal interconnection 11 and the source and drain regions 4 and 3. An additional contact layer is also provided within the additional contact hole so that the additional contact layer provides an electrical connection between the p+-type high impurity concentration region 6 and the metal interconnection 11 thereby to form a current path. The current path allows the holes generated in the channel region 5 to withdraw or discharge through the p--type low impurity concentration region 5a, the p+-type high impurity concentration region 6 and the additional contact layer to the metal interconnection 11.
The above third conventional SOI-MOS field effect transistor is capable of controlling the potentials of the source region and the channel region independently from each other because the current path for discharging the holes is formed separately from the source region. Further, the drain region 3 is directly in contact with the buried silicon oxide layer 2. This makes the transistor free from the problem with a large parasitic capacitance involved in the p-n junction. The above third conventional SOI-MOS field effect transistor is, however, engaged with the following other problems and disadvantages. As illustrated in FIG. 3, the p+-type high impurity concentration region 6 is formed outside the source region 4 to ensure the independent current path for discharging the holes. This means that the above transistor requires a large area, resulting in a difficulty in realizing a high integration of the transistor.
A fourth conventional SOI-MOS field effect transistor will be described with reference to FIGS. 4, 5A and 5B. This fourth conventional SOI-MOS field effect transistor is also disclosed in IEEE Transactions On Electron devices, Vol. 35, No. 8, August 1988, pp. 1391-1393. FIG. 4 is a plane view illustrative of this conventional SOI-MOS field effect transistor. FIG. 5A is a fragmentary cross sectional elevation view illustrative of this conventional SOI-MOS field effect transistor taken along an 5A--5A line of FIG. 4. FIG. 5B is a fragmentary cross sectional elevation view illustrative of this conventional SOI-MOS field effect transistor taken along a 5B--5B line of FIG. 4. A silicon-on-insulator layer made of silicon is selectively provided on the buried silicon oxide layer 2 so that the silicon-on-insulator layer is electrically isolated by the buried silicon oxide layer 2 from the silicon substrate 1. The silicon-on-insulator layer comprises p--type low impurity concentration regions 5a, a p--type channel region 5 between the p--type low impurity concentration regions 5a, a p+-type high impurity concentration region 6 laminated on a part of the p--type low impurity concentration region 5a, an n+-type source region 4 laminated on the remaining part of the p--type low impurity concentration region 5a, and an n+-type drain region 3 laminated on the p--type low impurity concentration region 5a. The p+-type high impurity concentration region 6 and the n+-type source region 4 are provided alternately in a channel width direction as illustrated in FIG. 4. A gate insulation film 7 is selectively provided on the channel region 5. A gate electrode 8 is provided on the gate insulation film 7. Side wall oxide films 9 are provided on opposite sides of the gate electrode 8. An inter-layer insulator 10 is provided which covers the source and drain regions 4 and 3 and the gate electrode 8 with the side wall oxide films 9. Metal interconnections 11 are provided which extend over the inter-layer insulator 10. Source and drain contact holes are formed in the inter-layer insulator 10 and over the source and drain regions 4 and 3 respectively and under the metal interconnections 11 so that the drain and drain contact holes reach the top surfaces of the source and drain regions 4 and 3 respectively as illustrated in FIG. 5A. Further, an additional contact hole is formed in the inter-layer insulator 10 and over the p+-type high impurity concentration region 6 and under the metal interconnection 11 so that the additional contact hole reaches the top surface of the p+-type high impurity concentration region 6 as illustrated in FIG. 5B. Source and drain contact layers electrically conductive are provided within the source and drain contact holes respectively so that the source and drain contact layers provide electrical connections between the metal interconnection 11 and the source and drain regions 4 and 3. An additional contact layer is also provided within the additional contact hole so that the additional contact layer provides an electrical connection between the p+-type high impurity concentration region 6 and the metal interconnection 11 thereby to form a current path. The current path allows the holes generated in the channel region 5 to withdraw or discharge through the p--type low impurity concentration region 5a, the p+-type high impurity concentration region 6 and the additional contact layer to the metal interconnection 11.
The above fourth conventional SOI-MOS field effect transistor is, however, engaged with the following problems and disadvantages. As well illustrated in FIG. 4, the source regions 4 and the p+-type high impurity concentration regions 6 are alternatively aligned in the opposite side to the drain region. This means that the area of the source region 4 is reduced. Namely, the width of the source region 4 is narrowed. The reduction in width or area of the source region results in the drop of the driving current of the transistor. In order to prevent the drop of the driving current of the transistor, it is effective to enlarge the size of the transistor. This enlargement in size of the transistor makes it difficult to realize the required high integration of the transistor. Further, as described above, the drain region 3 has a large area of p-n junction with the p--type low impurity concentration region 5a, for which reason a large parasitic capacitance is formed at the p-n junction between the drain region 3 and the p--type low impurity concentration region 5a.
In the above circumstances, it had been required to develop a novel semiconductor device with an improved contact hole structure free from the above problems and disadvantages.